Algorithmically Specialized Parallel Computers by Lawrence Snyder, Leah H. Jamieson, Dennis B. Gannon

By Lawrence Snyder, Leah H. Jamieson, Dennis B. Gannon

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HANSEN, AND CLARK D. THOMPSON 6. Conclusions This report discussed a VLSI implementation of a record-sorting stack. The implementation allows the sorting of n records, represented as (key, record-pointer) pairs, to be accomplished in 0(n) time. The design is cascadable so that the capacity of a single VLSI chip does not limit the amount of data which may be sorted. The algorithm, a parallel version of the classic bubblesort algorithm, was described, the overall chip organization and data flow were presented, and detailed circuits, layouts, and timing analyses were given.

With a processor per level arrangement, ARCHITECTURE FOR SEARCH TREE MAINTENANCE 45 this calls for 0(lgN) processors, as originally stated. Instead of storing between two and four keys per index node, the number of keys per node could be allowed to range between d and 2d. Tnis is simply a generalization of the 2-3-4 tree scheme, a variant of B+ trees [Com79] where 2d (instead of 2d - 1) is the allowed maximum number of keys. The corresponding insertion and deletion transformations are fairly obvious.

Key[2k+l]<7>) TOPCE , k«y[2k+l]) TT > TT TT ~~7 0 2 KEY BITS IN * OUT PHI2S1G CLOCKED EXCHANGE SIGNALS -*02 RPO (r«cPtr[2k]<0>. r«cPtr{2k«H]<0>) KECPTR BITS IN It OUT X RP1 . r«cPtr[2k+1]<1>) > RECPTR RECPTF BITS IN k OUT RP7 (r«cPtr[2k]<7>. 4. COL CeLl Structure. The controlling signals PUSH1 and P0P1 function as you would expect. The user asserts either PUSH or POP in proper phasing with clock phase 1 (PHIl). PHI1 is ANDed to produce PUSH1 or P0P1 which are then used to control writing into and reading from the RESST.

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